This invention relates generally to processing signals from imaging systems. More particularly, this invention relates to processing signals output from infrared sensors. Still more particularly, this invention relates to apparatus and methods for processing infrared sensor signals to guide a missile or the like toward a target.
The signal outputs from imaging infrared sensors are serial in nature. One of the problems encountered in using such sensors is the amount of time required to process the data output. The processing time is a critical factor in a high speed missile system flying toward a target.
U.S. Pat. No. 4,692,944, issued Sep. 8, 1987 to Masuzaki et al. discloses an image data processing system that includes an optical disk storage memory, a bit serial image data processing unit and an address calculation unit. The optical disk storage memory stores image data, and the bit serial processing unit processes the image data stored in the memory. The address calculation unit operates in parallel with the image data processing unit for calculating the address of the image data stored in the memory and for controlling the input and output of image data to and from the image data processing unit.
U.S. Pat. No. 4,694,398, issued Sep. 15, 1987 to Croteau discloses a digital image frame processor for processing two dimensional images produced digitally by an array of radiographic or ultrasonic detectors. Croteau's frame processor is designed to receive and correct sequential frames of digital images produced by a camera. The frame processor uses a forty-eight bit wide control word to enable several functions to be performed in parallel and incorporates bit-slice computer technology in an arithmetic logic unit.
U.S. Pat. No. 4,713,789, issued Dec. 15, 1987 to Suzuki discloses an image processor for processing X-ray transmission image data. Suzuki's image processor has a memory section that includes a plurality of storage means. The processor includes a control section that has means for generating address signals and applying the address signals to the corresponding storage means. Suzuki further discloses a processing circuit and a central control circuit that allow processing operations and storage in the memory means to be performed in parallel.
U.S. Pat. No. 4,727,423, issued Feb. 23, 1988 to Kaneko et al. discloses a video data processing circuit that includes a plurality of parallel-to- serial convertors and look-up tables. Kaneko et al. discloses reading video data in parallel from a plurality of video RAMS and providing the data to a corresponding parallel-to- serial convertor. The parallel-to- serial convertors store the video data in parallel. Each of the parallel-to- serial convertors serially outputs the stored video data to corresponding look-up tables. Each of the look-up tables converts the supplied video data into color data to be supplied to a selector, which outputs the caller data.
U.S. Pat. No. 4,745,469, issued May 17, 1988 to Waldecker et al. is directed to an optical apparatus for aligning vehicle wheels. Video cameras read the contour lines of a rotating wheel. Control of the video cameras and processing of the video data output from the video cameras is performed by a parallel processor-based computer system coordinated by sequential circuits.